In its simplest form, a digital electronic device that performs the
operation of modulo-two addition on two binary digits, the augend and the number
to be added, the addend. It is therefore also known as a binary adder. This operation is exemplified by the truth table shown in fig. a, where ∑ is the sum and Cº is the carry. From this it can be seen that binary addition may generate a carry to subsequent stages.
A fail adder has provision for inputs of addend, augend, and carry bits and is
capable of generating sum and carry outputs. These adders may be cascaded when
it is desired to add binary words greater than one bit in length by connecting
together the carry inputs and outputs of adjacent stages. The circuit shown in
fig. b, is a parallel adder operating on two 3-bit binary words (A0A1A2 and
B0B1B2) to produce a 3-bit result (D0D1D2) and a carry. The adder uses a
ripple-carry technique: the carry at each stage of addition must propagate or
ripple through the succeeding stages of addition in order to form the result.
A half-adder is an implementation of an adder that has provision only for input
of addend and augend bits and is capable of generating sum and carry outputs.
These devices cannot directly be cascaded as can full adders but may be made to
perform a similar function by including additional logic gating, as shown in
fig. c. This type of adder is relatively slow in operation.
See also BCD adder.