A type of clocked flip-flop consisting of master and
slave elements that are clocked on complementary transitions of the clock
signal. Data is only transferred from the master to the slave, and hence to the
output, after the master-device outputs have stabilized. This eliminates the
possibility of ambiguous outputs, which can occur in single-element flip-flops
as a result of propagation delays of the individual logic gales driving the
flip-flops.
