Hardware Communication Protocols/Hardware Organization :
Definitions and Explanation:
I/O devices, memory and CPU communicate with each other by using one or more communication buses.
1. Single-Bus Architecture:
The simplest computer uses a single communication bus. All devices are attached with this bus. Only two devices can communication with each other at one time. Some protocol is required to control the communication. Time is broken into clock cycles. Clock cycle is the time required to send a piece of information on bus. A special device bus arbiter decides which device will communicate in the next cycle. The selected device can communicate with any device if the device is connected to the system.
Usually, the bus is allocated to CPU to communicate with memory. CPU utilizes the bus more efficiently due to its high speed. I/O devices require the buss less frequently than CPU. But the communication needs of I/O devices are more time-critical. So the requests for the bus from I/O devices are given high priority than CPU. The process of taking the bus away from CPU and giving it to I/O device is called cycle stealing.
2. Multiple-Buses Architecture:
Multiple buses are used for the following reasons:
Parallelism:
Multiple communications are possible at the same time with multiple buses. For example, CPU can communicate with a port on one bus and a disk can communicate with memory on the other bus. The advantages of multiple buses are still limited. The reason is that most communications use either memory or CPU.
Performance Tuning:
Multiple buses enhances the performance of the system. Latest computer architectures use three types of uses:
- Peripheral Component Interconnect (PCI) bus is used to connect devices.
- Special memory bus is used for optimized communication between CPU & memory.
- Industry Standard Architecture (ISA) bus is connected to PCI bus to provide backward compatibility for older ISA devices.
3. I/O Control:
In the simple I/O control model, CPU communicates with I/O devices directly. CPU controls all details of device operation. This type of communication is only used in specialized, microprocessor-controlled, embedded systems.
In PC model, CPU communicates with a device controller. A signal from CPU to device controller may start a read operation from a device. The detailed commands of read operation are performed by device controller. CPU can perform other processing in the mean time. Each I/O controller is designed to handle a particular kind of device.
Some sophisticated system use an additional level of I/O control. CPU communicates with an I/O channel. This channel communicates with an I/O Control Unit. I/O channels are more sophisticated than I/O controllers and may have their own CPU. They execute channel programs loaded in the main memory or channel's memory.
4. Ports and Memory-Mapped I/O:
CPU must communicate with I/O module to perform any I/O operation. An I/O module contains one or more registers. The communication is done by reading or writing to these registers. The I/O module sets the values of registers to communicate with CPU.
CPU. access the module registers in two ways:
1. Port I/O:
In port I/O, a limited number of instructions provide I/O capability. One instruction operands is an I/O port number. I/O operation is applied to I/O module identified by that port.
2. Memory-Mapped I/O:
In memory-mapped I/O, any instruction that accesses memory may access an I/O module. A part of memory space is allocated to I/O modules. It is a disadvantages in system with limited address space.
5 Module Registers:
Different I/O modules have different types and number of registers. A simple module for input device may have only two registers; one for data and one for control information. The data register stores the value and control register contains bits to command I/O module. The bits may be used to enable the device, reset the device or begin a read operation etc. Some bits are used to signal operation completion, device ready or error conditions etc.. The modules for complicated devices contains more registers.
6. Busy Wait I/O:
Busy wait is a protocol for communication between I/O module and CPU. CPU issues a signal to I/O module to start I/O operation. In output operation, data is transferred to data buffer of the module. CPU repeatedly checks for the completion of the command. When it is completed, status information is checked to verify the success of the operation. In input operation, data is transferred from the module buffer. Busy wait I/O is inefficient because processes can make no headway while CPU waits for the completion of I/O operation.
7. Polled I/O:
In polled I/O, CPU continues to execute different processes in the system after initiating I/O operation. CPU checks for the completion of I/O operation after brief intervals. Polling is more efficient. The disadvantage is that the processes are interrupted when CPU checks for the completion of I/O operation.
8. Interrupt I/O:
An interrupt can be sent to CPU when I/O operation is completed. In this way, CPU continues to execute other process until it gets an interrupt from I/O module. It provides parallelism but adds complexity in the code.
9. Direct Memory Access (DMA):
Interrupt-driven I/O is more efficient than programmed I/O. It still requires the active intervention of the CPU to transfer data between memory and the I/O subsystem. Any data transfer must traverse a path through the CPU.
As shown in the diagram, when using programmed I/O or interrupt-driven technique the CPU is tied up in managing an I/O transfer. A number of instructions must be executed for each I/O transfer. When large volumes of data are to be moved, a more efficient technique is required known as Direct Memory Access (DMA).
DMA involves an additional module on the system bus:
The DMA module above is capable of mimicking the CPU and indeed of taking over control of the system from the CPU. The technique works as follows:
When the CPU wishes to read or write a block of data it issues a command to the DMA module by sending to the DMA module the following information:
1. Whether a read or write is requested.
2. The address of the I/O device involved.
3. The starting locations in memory to read from or write to.
4. The number of words to be read or written.
The CPU then continues with other work.
It has delegated the I/O operation to the DMA module. The module will take care of it. DMA module will then, transfer the entire block of data one word at a time directly to or from memory without going through CPU. When the transfer is complete, DMA module sends an interrupt signal to CPU. CPU is only involved at the beginning and at the end of the transfer. DMA works while CPU is idle i.e. not using the system bus. It is called cycling stealing.
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